Here are some examples of how to set the hysteresis voltage of a comparator.
Conditions: VDD = 3.3 V, VREF = 1.4 V, hysteresis width = 6 mV, rise detection voltage 1.650 V

1) R3 rate
In order to minimize the influence of the input leakage voltage, it is necessary to pass a current of at least 0.5 µA to R₃. The current flowing to R₃ is (V_REF − V_OUT)/I_R3, with V_OUT = 0 V or V_OUT = V_DD, so you can obtain the rate by calculating R₃ = V_REF/I_R3 or R3 = (V_DD − V_REF)/I_R3.
The smaller of the two results is used. When V_DD = 3.3 V, V_REF = 1.4 V and I_R3 = 1 µA, the two resistance rates are 1.4 MΩ and 1.9 MΩ, so our choice here is 1.4 MΩ.

2) Hysteresis width
V_HB will be 6 mV in this case.

3) R₁ rate
R₁ = R₃ (V_HB/V_DD)
R₁ = 1.4M (6m/3.3) = 2.55 kΩ

4) VTHR
Set the rise detection point of V_THR so that V_THR > V_REF(R₁ + R₃)/R₃ is satisfied. It will be 1.650 V in this case.

5) R₂ rate
R₂ = 1/(V_THR/(V_REF⋅R₁) − (1/R₁) − (1/R₃))
= 1/(1.65/(1.4⋅2.55k) − (1/2.55k) − (1/1.4M))
= 14.4 kΩ

6) Result
The rise and fall time and hysteresis width are as follows:
Rise time: V_THR = V_REF⋅R₁(1/R₁ + 1/R₂ + 1/R₃)
Fall time: V_THF = V_THR − R₁⋅V_CC/R₃
Hysteresis: V_HB = V_THR − V_THF = R₁⋅V_CC/R₃

This might happen when you create your own circuit and set the common-mode input voltage of the comparator to a value that exceeds the level specified in our data sheet (i.e., a value that approaches VDD). Please be aware that the common-mode input voltage of the S-891 series and S-892 series is not full range from VSS to VDD.

Yes, you can. Phase compensation is built in all operational amplifiers except for the S-89402/89403 to enable use at a gain of +1. The S-89402/89403 implements phase compensation to enable stabilization at a gain of 5 or more.

It’s the product of the gain and the bandwidth.

We recommend using our S-8953 series, S-892 series and S-8951 series comparator products instead. The reasons are:

1. The rise time and fall time are shorter compared with an operational amplifier with the same current consumption because phase compensation capacitance is not used.

2. The current consumption may increase if you use an operational amplifier as a comparator. For instance, if you use the S-8943 (operational amplifier) as a comparator, the current consumption may increase up to 3 to 6 µA when the output is saturated on the VDD side. We therefore recommend using the S-8953, not the S-8943.

This problem is inherent to series S-8520/8521.
This IC has a soft start circuit that ensures slow startup of the output voltage by gradually increasing the Vref voltage from 0 V to the reference voltage and minimizes rush current at startup. However, the Vref voltage and VOUT pin voltage go 0 V the moment voltage starts dropping. Any rise in the output voltage is controlled until the Vref voltage keeps a certain level of voltage because normal control of the output voltage is not available. This enables the output voltage to start up at a certain Vref voltage, to be instantaneously increased. At this time rush current flows. As one of measures, it is recommended that TR2, 3, R1 to 4 and C1 be added.

Basically, the same effect as soft start can be obtained by charging CL from VIN via R4 while the ON/OFF switch is forcibly turning off TR1 in the UVLO circuit when LO→HI.
Configure the IC so that off time is obtained in the UVLO circuit using C1 and R1 (when the configuration is achieved by microcomputer, use it.) or design the IC so that gradient of a rise in the OUT voltage can meet soft start via R4 In addition, rush current can be decreased by turning on TR2 and TR3, flowing current of (Vin-Vout)/R4 through OUT and charging CL.

Different from the PWM/PFM switching method, the PWM method ensures stable switching frequency and gives easy determination of frequency of external noise and also easy assembly of the filter. On the contrary, the PWM/PFM switching method is extremely superior in efficiency during moderate and light load. The following is efficiency data of PWM/PFM based S-8521B50 and PWM based S-8520B50 for your reference.

The current limit circuit is to protect external FETs against breakage due to overheat. When output is shorted and external FETs are off, current passes from the input pin via the external coil and the Schottky diode as well to the output pin. In other words, DC current flows.

Theoretically, as you know, when output is shorted, the S-8340 stops its operation and turns the Tr off. Then, nearly the same input voltage is applied to both external coil and Schottky diode and large current exceeding the power dissipation. This may damage these elements because of overheat.

Actually, however, any of the following elements such as
· Input power supply resistor,
· Diode resistor, and
· Output short resistor (contact resistance and wiring resistance)

is involved in inevitable overheat. Voltage (loss) to be applied to each element varies depending upon the ratio

among resistances. Because of it, the most sensitive element will be thermally damaged.

Only leakage current may flow. The IC current consumption when the VDD pin is open causes VDD to be equal to VSS and CONT to be open. There is a several MΩ routes from VOUT to VDD via a parasitic diode, however, current does not flow to the VDD pin because of the voltage relationship VOUT < VDD.

+5 V output can be obtained by using the S-8357E. The input voltage, however, must be fixed to 5 V. Figure 1 shows an example of a circuit to convert voltage from positive to negative.

A process opposite that shown in Figure 1 must be done to convert voltage from negative to positive.

A configuration shown in Figure 2 can be achieved with the S-8357E, but a positive voltage must be set as the negative voltage reference. Output voltage = (S-8357E set voltage) − | Input voltage | , so resistance must be set such that the set voltage of the S-8357E is 10 V. The input voltage must be fixed for this reason.

The EXT amplitude ranges from GND to the power supply voltage of the internal circuit of series S-8355/56/57/58.
Power supply of the internal circuit in normal types B,H,F and N for series S-8357/8 is supplied from the VOUT pin.
Hence, the EXT output amplitude ranges from GND to VOUT; whereas the power supply of the internal circuit in VDD discrete types E, J, G and P for series S-8357/8 and S-8355/6 is supplied from VDD pin. Hence the EXT output amplitude ranges from GND to VDD. For instance, when VIN voltage is supplied to the VDD pin, the EXT output amplitude ranges from GND to VIN.

External Transistor Peripheral Circuit

i. When rush current that flows from the input power supply results in no problem during power on:
Cut off SWR from VIN during power off.
Then, turn on TR3 and discharge Cout on RC because the TR2 is turned off during power off.

ii. When rush current that flows from the input power supply results in a problem during power on:
Cut off VDD of the IC and GND side of the external resistor during power off.
Then, turn on Tr5 and discharge Cout2 on RC because Tr3 and Tr4 are turned off during power off.
Dual input of power ON positive logic and negative logic is needed.
2 transistors and 1 capacitor are added to the circuit configured in Figure 2.

Any soft start function is added to prevent overshoot of the output voltage at startup of boosting and rush current during boosting. The soft start method adopted in this IC is designed to slowly increase the reference voltage. Waveform obtained at the time of soft start in series S-8357B30 is shown below. As the figure shows, output voltage Vout is slowly increased in connection with the gradual rise in the reference voltage Vref inside the measurement circuit from 0 V. The rise time is determined inside the IC per oscillating frequency [Note: the dotted line Vref given in the waveform graph is the value calculated by converting reference voltage Vref to output voltage Vout level (Vref=VREF´(R1+R2)¸R2)].

The rise in Vout near Vin is attributed to supply of current from VIN to VOUT via L and SD of the measurement circuit.

Measurement Circuit

Any soft start function is added to prevent overshoot of the output voltage at startup of boosting and rush current during boosting. Soft start methods are as follows:

i. establish a current limit in switching current.
ii. slowly increase the reference voltage (series S-8353/54/57/58).
iii. impose “ON duty” limits at the time of startup.

S-8353/54/55/56/57/58 adopts the method of ii.

There is no problem.
In series S-8353/4, the power of the IC is supplied from Vout side. Basically, any fluctuation of Vin voltage does not directly affect the IC.

[Reference]
Both S-8353D and S-8354D are equipped with power supply pin VDD and called VDD discrete regulators. These ICs are not equipped with a diode that is forward connected from VOUT to VDD. Hence, each IC is free of a malfunction you questioned.

Effective measures are as follows:

i. Increase the output capacitance (Cout).
ii. Use series S-8357N (600 kHz-products).
iii. Insert an LC filter after the SWR. This leads to an increase cost because a coil of DCR of several tens of m ohm higher than Ioutmax 500 mA is needed.

A method to increase value “L” of the coil from 22µH to 1mH is introduced here. This method ensures that the switching frequency is higher than the audio frequency. Be sure that the increased value “L” decreases the maximum load current to be obtained by the switching regulator. If noise remains, replace the current coil with a new one that deadens noise.

Use a large capacitance coil;

Use a coil with unshielded construction.

Coil noise results from any shrinkage of ferrite due to any variation in the magnetic field and is amplified with resonance of the coil and PCB. Coil noise can be minimized by enhancing the coil mount design.

As you have indicated, it is true that the resolution of the electronic volume does not satisfy 8 bits when the S8330A26FS runs at 14 to 26 V.
Linear Error Aspect:
There are 3 definitions of a linear error used in ABLIC’s specifications. To facilitate your understanding, brief and clear explanation is given to each definition as follows.

(1) Specifications covering 0 to 127 of the electronic volume data (at ±23.5 mV)
This is a linear error obtained by connecting the actually-measured output voltage when electronic volume data is 0 and the actually-measured output voltage when electronic volume data is 127, respectively, with a straight line. It corresponds to the difference between the measured value and the calculated output value in any bit of 0 to 127 of the electronic volume.

(2) Specifications covering 128 to 255 of the electronic volume data (at ±23.5 mV) This is a linear error obtained by connecting the actually-measured output voltage when electronic volume data is 128 and the actually-measured output voltage when electronic volume data is 255, respectively, with a straight line. It corresponds to the difference between the measured value and the calculated output value in any bit of 128 to 255 of the electronic volume.

(3) Specifications covering 0 to 255 of the electronic volume data (at ±93.8 mV) This is a linear error obtained by connecting the actually-measured output voltage when electronic volume data is 0 and the actually-measured output voltage when electronic volume data is 255, respectively, with a straight line. It corresponds to the difference between the measured value and the calculated output value in any bit of 0 to 255 of the electronic volume.

A switching regulator specifically for use in creating negative voltage is not available. However, negative voltage can be output using a step-up switching regulator.

Inverting Switching Regulator Circuit

The start circuit is not needed because power supply is supplied from V_DD pin to the IC. Set voltage V_IN to 9V-|V _CC. When V_CC is -2 V, -3 V and -5 V, be sure to connect V_OUT of S-8353D20MC, S8353D30MC and S-8353D50MC to GND without attaching RA, and RB. The external resistor Rb must be 60 ohm or more and RE must be 6 k ohm or less. The larger RE becomes, the smaller the invalid current flowing RE and Rb and also the better the efficiency. A large value for RE raises efficiency due to the reduction of reactive current for RE and Rb. Too large value of RE lowers efficiency due to the large switching loss of the external transistor(Tr). Choose a suitable value of RE under the operating conditions.

It may be attributed to the continuous mode the IC is entered. Conditions to enter the continuous mode are determined by input voltage and output voltage. Once the continuous mode is entered, the duty ratio does not go up at heavy load.

Figure 1: Continuous Mode Based On the PWM Method

One of possible reasons is marginal setting of output current drive, in particular, when a drop appears at low Vin. This drop greatly affects hFE(small) and base resistance Rb value(large) of an external bipolar transistor. In addition, the drop affects value L (large) of the inductor and frequency (high) of the switching regulator to a certain extent. If output voltage drops at large output current despite sufficient output current drive, it results from the load stability characteristic in itself. The following are probable reasons:
(1)PCB patterns
It is known that any drop in output voltage at large output current range greatly differs depending upon PCB patterns. So, you are asked to check whether or not the drop depends on PCB patterns.
(2)Output capacitance
When (1) is deemed ideal, another probable reason is due to output capacitance. If improper output capacitance is selected and used, there may be an apparent drop in output voltage at large output current. For instance, the drop is attributable to (2) if parallel connection of two additional output capacitors allows the drop to be minimized. Control of the switching regulator is extremely affected by, especially, ESR of output capacitor. As you are well aware of, it is experientially effective to minimize the drop in output voltage at large output current by adopting a low ESR tantalum electrolytic capacitor and increasing the output capacitance value.

Basically, up to 9 V can be impressed to input voltage (CONT) pin and output voltage (VOUT) pin, respectively, without causing a problem because voltage of up to 9 V is within the voltage range that warrants normal functions of the IC.
[Reference]
Absolute maximum rating voltage of 11 V warrants that it can safeguard the IC against its breakage even when DC is impressed to the IC. However, operation of the IC is out of the warranty.
In other words, impression of 11 V would lead to an abnormal flow of current or an ON error (EXT=VDD) in the external transistors.

When it is used as resistance division, gate charge current will flow from VOUT to EXT to FET in popular FETs. This affects voltage at the VOUT pin. Please avoid this type of use.

The following ABLIC’s switching regulators equipped with their own power supply pins allow the output voltage to be controlled by resistance division:

• Types D and J for S-8353 series
• Types D and J for S-8354 series
• All of S-8355 series
• All of S-8356 series
• Types E, J, G and P for S-8357 series
• Types E, J, G and P for S-8358 series
• Types B and D for S-8340 and S-8341 series

Increase inductance value of the coil you use, increase the switching frequency and decrease the “Iout” value. Check the peak current using the GTSCAT ^Note* (circuit simulation).
^Note* : GTSCAT simulates a plurality of characteristics of ABLIC’s switching regulator peripheral circuits. Please download it from ABLIC homepage.
URL: http//www.ABLIC.co.jp/compo/compo.htm

An LC filter suppresses voltage variation of the power supply.
When there is no LC filter, ripple voltage variation of the magnitude equal to the series resistance of the power supply multiplied by the on-current appears at the power supply.
But if an LC filter is added to the circuit, it suppresses the ripple voltage variation, since the on-currnt of the switching regulator is provided from the capacitor which is charged by rather tranquil current, which reslts from the nature of a inductor.
However please pay atention to the following points.

· The input voltage, which is taken after the LC filter, to the switching regulator becomes easy to vary.

· When the equivalent series resistance “L” is several hundreds of mW or more, efficiency may worsen due to overheat caused by the equivalent resistance and input current.

· This is because the RC filter is formed by the equivalent series resistance and “C,” the input voltage of the switching regulator (after LC filtering) is lower than the power supply voltage (before LC filtering) and eventually output amperage will be decreased.

An aluminum electrolytic capacitor can be used as Cin without causing a problem. Select a large capacitance capacitor (Cout) with low ESR (Equivalent Series Resistance) to level and smoothen the ripple voltage output capacitor. The capacitance is 10mF min. It is recommended to use a tantalum electrolytic capacitor that is superior in low temperature and leak current characteristics. For example, series F93 is deemed ideal.
When the aluminum electrolytic capacitor is used as Cout, the IC may malfunction depending upon its operation conditions and wiring. It is recommended to use a tantalum electrolytic capacitor as practical as possible. When an aluminum electrolytic capacitor is used, be sure to validate influence of ripple and spike noise on your actual product according to the precautions listed in ABLIC’s datasheet. In addition, please note that attaching a ceramic capacitor of 0.1 mF or thereabouts between VOUT-VSS in the vicinity of the IC may avoid a malfunction.

Choose a value for external parts by GTSCAT ^Note* simulation.
^Note* GTSCAT simulates several characteristics of ABLIC’s switching regulator peripheral circuits. Please
download it from ABLIC homepage.
URL: http//www.ABLIC.co.jp/compo/compo.htm

Refer to the following table showing the relationship between major characteristics of switching regulators and external parts.

Refer to the following table showing the relationship between major characteristics of switching regulators and external parts.

Refer to the following table showing the relationship between major characteristics of switching regulators and external parts.

Follow the procedures given below:

– Check the maximum rated current of the coil you use and be sure that it is more than its peak current (failure to do so may lead to magnetic saturation resulting in worsening efficiency).

– Select an external diode with low VF characteristic and speedy first-recovery time.

– Select low ESR of the output capacitance COUT that greatly affects the efficiency.

– Please note that the ON resistance of an external switching transistor differs depending on the value of base resistance RB (resistance between EXT pin and external transistor base) and high RB value worsens efficiency.
Also please note that low RB value leads to an increase in current consumption and may worsen the efficiency

As long as the output signal is high, the CD pin stays at the GND level because capacitance C is discharged, so a reset does not occur even if the CD pin is made low. To activate external reset, forcibly make the OUT pin low. The following shows an example of an external reset circuit.

The delay time (power-on clear time) can be calculated by substituting the constant to the following equation when the power-on clear circuit is structured by series S-808XXCN or S-1000NXX:

Caution: To avoid oscillation: Use a resistor of 75 kΩ or lower for the S-808XXCN. Use a resistor of 75 kΩ or lower and capacitor of 0.01 µF or higher for the S-1000NXX. When a capacitor is not connected to the S-1000NXX, use a resistance of 800 Ω or lower. The S-809XXC Series and S-801 Series each have a built-in delay circuit, so a power-on clear circuit can be easily configured. See the respective data sheets for details. The detector may momentarily output “H” in an uncertain area at the minimum operating voltage or less, depending on the startup speed of the power supply voltage.

Since the output is configured of a MOSTr, device destruction due to thermal runaway as in bipolar transistors can be avoided. However, note that the devices will be destroyed if a current that surpasses tolerable losses of the package flows due to a short circuit with VDD or to connection of a super capacitor. Nch Open Drain Short Circuit with VDD2

Nch Open Drain Short Circuit with VDD2

Using the S-80960AL as an example, a case in which tolerable losses are surpassed is explained. Based on the Iout-Vds characteristic in the data sheet, a current of about 50mA flows to Output NchTr in case 5V is impressed to the output when VDD = 6V. The loss at this time will be P = 5(V) x 50(mA) = 250mW, exceeding the absolute maximum rating of 150mW. In a worst case, the devices may be destroyed.

The operation when Vin fluctuates near detection and release voltages is explained in Fig. 1 using the output of CMOS (active L) as an example.

1. OUT outputs ‘L’ and becomes ready to detect when VDD falls below -Vdet. Since the comparison voltage with VDD is changed to +Vdet, a release state is not set if voltage VDD is below +VPET even when VDD rises and fluctuates near -Vdet. (During period “A”)

2. The comparison voltage with VDD is changed to -Vdet when VDD rises and exceeds +Vdet. Therefore, detection is not performed even when Vin fluctuates near +Vdet unless it lowers below -Vdet. OUT will output ‘H’ after a release delay time (td) and will change to a release state. (During period “B”)

The condition of the output will become high impedance in case of open drain output.

Generally, the discharging diode D discharges charges in the release delay capacitor through it in a CR resetting circuit illustrated in Fig. 1, to ensure a sufficient release delay time during release. The S-809XXC discharges charges in the release delay capacitor in the discharge circuit inside the IC except during release delay operation as shown in Fig. 2. Therefore, an external discharge diode is not required. Figure 1: Function of Discharging Diode (Ordinary CR resetting)

A reset signal cannot be generated even when Pin CD is forcibly connected to GND by an external SW as shown in Fig. 1. A circuit configuration that generates a reset signal cannot be obtained even if Pin CD is forcibly connected to GND as illustrated by the block diagram in Fig. 2. As shown in Fig. 2, the level of Pin CD is normally a GND level. Triggering occurs only when VDD exceeds the release voltage, causing charging of the capacitor for release delay connected to Pin CD to start, which in turn raises the voltage. The level of Pin OUT will become Hi (HiZ for Nch products) when the voltage reaches a certain level, to provide a release delay time. After clearing resetting, the capacitor for release delay will be discharged immediately to reset it to the GND level.

If a high output level at a minimum operational voltage presents a problem, it can be solved by externally mounting a Pch transistor.

In case VDD lowers below the detection voltage, the Nch open drain output will turn on and the level of OUT will become low. When VDD lowers below the threshold value of the external PchTr, the external PchTr will turn off and Rup resistance will be separated from VDD, so that VDD lowers below the MIN value of operational voltage of the voltage detector. Therefore, the level of OUT will not become high (VDD) even though NchTR no longer operates. As a precaution when selecting an external PchFET, select one whose threshold voltage is higher than the minimum operational voltage of the voltage detector. Note that the output (OUT) will not become VSS in this case.

Shown below are examples of circuits that illustrate how to widen the hysteresis range in an application that uses a detection voltage alteration circuit.

Looking at Figure 1, Diode D1 will be needed to prevent a reverse current from RUP to R2 and to R3. Let us assume that the detection voltage in IC setting to be -Vdet, hysteresis in IC setting, VHYS, and forward voltage of D1, Vf. When detection is made, the voltage obtained by dividing VDD by R1 and R3 is compared with the detection voltage in IC setting,

When VDD lowers below the operational detection voltage and the level of the output becomes low, the circuit illustrated in Fig. 1 will become equivalent to the circuit shown in Fig. 3.

Figure 3: Equivalent circuit when VDD is below operational detection voltage

In a detection state, R2 and Vf are input to R3 in parallel and the operational release voltage and operational hysteresis range will become as follows

The same values can be used with the circuit illustrated in Fig. 2 also.

As a precaution for R1 and R2 setting values, R1 < 75kΩ should be set as a countermeasure for oscillation. Detection voltage will deviate by current consumption x R1 voltage the larger R1 is, to deteriorate the detection accuracy. Therefore, set values for R1 and R2 are recommended to be as small as possible (about several kΩ).

Shown below is an example of a circuit that illustrates how to widen the hysteresis range by increasing the release voltage only while maintaining the detection voltage as set in the IC when power sources for input and output are different.

Figure 1: Nch Open Drain Output
Output is pulled up to VDD2 where VDD2 > VDD1

Diode D1 will be needed to prevent a reverse current flowing from VDD2 to VDD1. Assuming that the detection voltage in IC setting to be -VDET, hysteresis in IC setting, VHYS, and forward voltage of D1, Vf:

As a precaution for R1 and R2 setting values, R1 < 75kΩ should be set as a countermeasure for oscillation. Detection voltage will deviate by current consumption x R1 voltage the larger R1 is, to deteriorate the detection accuracy. Therefore, set values for R1 and R2 are recommended to be as small as possible (about several kΩ).

In case a voltage detector with a desired hysteresis range is not available, increase the release voltage by installing an external circuit, to widen the hysteresis range. The following illustration shows an example of a circuit that widens the hysteresis range.

Figure 1: Nch Open Drain Output
Output is pulled up to VDD

Assuming that the detection voltage in IC setting in the circuit illustrated in Fig. 1 to be -V_DET and hysteresis range in IC setting, V_HYS:

Figure 2

As a precaution for R1 and R2 setting values, R1 < 75kΩ should be set as a countermeasure for oscillation. Detection voltage will deviate by current consumption x R1 voltage the larger R1 is, to deteriorate the detection accuracy. Therefore, the set values for R1 and R2 are recommended to be as small as possible (about several kΩ).

There are two cautions when the pull-up resistance is increased:
Caution 1: Output voltage (Hi is output by pull-up resistance) when the voltage detector is off is lowered by an off-leak current. Caution 2: The output pin (input pin in second stage) becomes less robust to noise.

Figure 1: Voltage detector is off

Caution 1:
Fig. 1 illustrates the circuit of the Nch open drain output product. When the voltage detector is off, M1 turns off and Pin OUT outputs Hi (VDD) due to the external pull-up resistance Rup. At this time, Off-Leak Current ILEAK flows to M1, generating a voltage drop (Vdwn) of ILEAK x Rup at both ends of the pull-up resistance Rup. Thus, the voltage at Pin OUT will be as follows:

Vout = VDD −Vdwn = VDD − I LEAK × Rup

Using the S-808XXC as an example, the data sheet shows maximum ILEAK = 0.1µA. If Rup = 10MΩ, the voltage drop Vdwn at Rup will be:

Vdwn = 0.1(µA) × 10(MΩ) = 1(V)

The voltage Vout will be low as much as 1V compared with VDD so that Level Hi may not be recognized at the input of the connect-to IC.

Caution 2:
The impedance at Pin OUT will be high and the output pin will become less robust to noise and error setting may be applied.

Based on the foregoing cautions, the recommended Rup value is 100kΩ.

There are two cautions when the pull-up resistance is decreased:
Caution 1: Output pin voltage is increased during detection.
Caution 2: Current that flows in the pull-up resistance increases (Increase in current consumption as viewed from the battery side during detection).

Caution 1:
When the level of VDD lowers below the detection voltage, OUT = ‘L’ is output and the internal output NchTr turns on. At this time, voltage that is obtained by dividing power supply voltage VDD by the pull-up resistance and ON resistance of NchTr is output to the output. Therefore, Level ‘L’ increases when the pull-up resistance is too small.
Using the case of VDD = 2.4V in the S-80860CN as an example, the difference in output voltage of Level ‘L’ between 10kΩ and 1kΩ in pull-up resistance between OUT and VDD is explained. As shown in Figs. 2 and 3, output voltage is calculated based on the data at the intersection point between the Vds-Id characteristic of M1 (described in data sheet of S-808XXC Series) and load curve of pull-up resistance. Fig. 3 is an enlarged diagram of the shaded part in Fig. 2. Reading output voltage based on the data at the intersection point between the Vds-Id characteristic (blue curve) and load curve of 10kΩ pull-up resistance (red curve) in Fig. 3, the output voltage is about 20mV and is about 200mV with the 1kΩ pull-up curve (aqua color). Level ‘L’ with 1kΩ is about 10 times higher compared with 10kΩ pull-up. No problem will arise if this Level ‘L’ is a level that is recognized as ‘L’ at the input of the connected-to IC of the voltage detector. However, if the pull-up resistance value is too small and Level ‘L’ is too high, the level of ‘L’ will no longer be recognized at the output of the connect-to IC.

Caution 2:
As in Caution 1, reading the output current (current that flows through Rup) based on the data at the intersection point between the load curves of pull-up resistances and Vds-Id characteristic shown in Fig. 3, the output current is about 0.22mA at 10kΩ compared with about 2.2mA at 1kΩ, or about 10 times higher. The current consumption as viewed from the battery side during detection operation increases.

Based on the foregoing cautions, the recommended Rup value is 100kΩ.

ABLIC’s datasheet describes that an error pulse generates in the power-on reset circuit due to an uncertain area characteristic at the sharp rising edge of the power supply. See the figure given below. To take an easy and simple preventive measure against occurrence of an error pulse, it is only necessary to add a resistor to the power-on reset circuit. The following are an error pulse generation mechanism and preventive measures.

Error Pulse Generation Mechanism

Figure 1: Power-on Reset Circuit Listed in the Datasheet

In general, an uncertain area exists in the V/D. Further reduction in V/D input voltage “Vin” fails to flow “Rup” current, and eventually V/D output voltage “Vout” becomes not inherent LO but HI. The power-on reset circuit leads to the delay in the rise in V/D input voltage “Vin” by RC time constant at the time of powering on Vdd and also leads to the delay in the time release signal necessary to reach V/D release voltage “Vdet+.” However, V/D input voltage “Vin” passes through the uncertain area which does not flow current of the output pull up resistance Rup. This results in output of an error pulse as a release signal.

When the load is low, the transistor in the regulator must be of high impedance. There is, however, leakage current in the transistor, so control is not possible when the load is low. As a result, the output voltage increases (for specific values, see the data sheets of respective products).
This symptom cannot be avoided because it is caused by the series regulator configuration. Countermeasures, such as connecting a dummy load resistance, must be taken.

The functions of these pins are the same.
Two VIN pins are provided for promoting heat loss.
The input voltage of the S-812CXX Series is high at 16 Vmax. and the power dissipation of the IC is large,
causing a high temperature. Connect two VIN pins to the board.

Series S-817 is superior in input stability and keeps output variation under 5 mV typ. even when output current of Iout=1µA flows during light load. Consequently, the S-817 can be used as a reference voltage of A/D converters and similar devices if input voltage varies. Namely, it covers applications without flowing output current of the regulator.

Series S-817 is an internal phase compensation regulator. It ensures stable operations even when ESR of
the output capacitor is low. This enables to use a low ESR ceramic capacitor. Operating conditions of the
ceramic capacitor are:
Capacitance is 0.1µF or more;
ESR is 30 ohm or less.

need it depending on their own operating conditions.

Briefly explained, the output level enables the phase to be compensated using the output capacitor’s ESR.
This ensures stable operations even if output load varies.
The output capacitor allows customers to connect a ceramic capacitor or which current is 0.1µF and ESR is 30 ohm or less.

Necessity of a capacitor at the input level will be determined based on the input power characteristics. The valid data confirmed on your actual product is of importance.

Voltage regulators need an input capacitor or output capacitor at the output level, whereas at the input level, they may not need it depending on their own operating conditions.

Briefly explained, the output level enables the phase to be compensated using the output capacitor’s ESR.
This ensures stable operations even if output load varies.
The output capacitor allows customers to connect a ceramic capacitor or which current is 0.1µF and ESR is 30 ohm or less.

Necessity of a capacitor at the input level will be determined based on the input power characteristics. The valid data confirmed on your actual product is of importance.

A ceramic capacitor can be used in the S-814 as an output capacitor. The S-814 is an internal phase compensation regulator that ensures stable operation even when ESR of the output capacitor is low. This allows to use a low ESR ceramic capacitor. Operating conditions of the ceramic capacitor are:
Capacitance is 0.47µF or more;
ESR is 10 Ω or less.

There is a possibility of output being oscillating when using a ceramic capacitor or an OS capacitor whose ESR is low.

To make stabile operation of the S-816 series, it is necessary to use a capacitor that ensures the optimum range of ESR (EQUIVALENT SERIES RESISTANCE). Higher or lower ESR than the specified range may destabilize output and oscillate the circuit. It is recommended that a tantalum electrolytic capacitor be used.

When using a ceramic capacitor or an OS capacitor, it is necessary to add a resistor (in substitution for ESR) to the output capacitor in series.
Resistance of the resistor to be added ranges from 0.1 Ω to 5 Ω or thereabouts. It differs depending upon operating conditions. Be sure to determine it after making a sufficient assessment. The recommended value is approx. 0.3 Ω.

An aluminum electrolytic capacitor may cause oscillation due to increased ESR at low temperatures.
It is necessary to make a sufficient assessment including temperature characteristics.

Noise generating at the regulator output pin at an uncertain interval of several ms to seconds may be attributed to popcorn noise emitted from the external bipolar transistor.

Popcorn noise will be emitted from the bulk operation-type bipolar transistor. Generation of such noise is not attributed to CMOS based S-816 series.

For example, the S-817 series has a short current limit circuit to safeguard the output transistor from shortcircuiting between VOUT-VSS pins. The short current limit circuit controls output current for Vout voltage and keeps output current constant at 40 mA or thereabouts even when shortcircuiting between VOUT-VSSp pins occurs.

Figure 1

Please note that the short current limit circuit does not protect thermal shutdown. Taking into consideration requirements for input voltage and load current including shortcircuit conditions so that any loss in the IC does not exceed the maximum power dissipation.

Figure 2

The short current limit circuit starts functioning to safeguard the output transistor when large current flows and the difference between input and output voltage is large even if not shorted.

A voltage regulator has an output transistor (also called a pass transistor) using a low ON-resistance transistor. This transistor minimizes the drop of voltage (dropout) of the voltage regulator. Series S-814 and S-818 are low dropout voltage regulators. The dropout voltage to flow current of 60 mA is 0.17 V (typ.) for both series of 5-V output products.

Low dropout voltage regulators are used in applications where the difference between the input and output voltages is low as well as necessary current is large.

For example, lowdropout voltage regulators meet the requirements for maximizing the battely voltage limit. This is because they can supply constant current even when the input voltage (battery voltage) drops and approximates the output voltage. A reduced dropout voltage brings the same effect as the battery life is prolonged.

The device will not be damaged if you leave input pins open but it makes the performance unstable.
The characteristics of the operational amplifier are also affected on the user side. Thus we recommend you to implement the following procedure.
Operational amplifier:
Set a voltage follower configuration and connect the input Vin+ to VSS.
Comparator:
Connect Vin+ to VSS and Vin− to VDD.
If, however, you want to use only one circuit of a dual product, we recommend using a single product.

The input offset current is in the order of 1pA because it flows through the gate oxide of the MOS transistor. However, it is difficult to measure it correctly because of the leakage current of the package pins or because the measurement accuracy is in the pA order. Under our test conditions, the S-891 series and S-892 series are tested whether the maximum value of the input offset current is 50 nA or less. Other mini analog products are tested whether this maximum value is 10 nA or less.

The data sheet describes that the maximum rating of the input voltage for mini analogs is VSS to VDD.
This is the range of input voltage that is guaranteed by our reliability test data.

However, the device should not be damaged even if you apply an input voltage a little outside this range. How much outside this range is allowable can be defined as follows:
As described in the data sheet there is an off-transistor (NMOS) connected between the input pins and VSS for protection against ESD. The current increases when the input voltage falls below VSS – 0.7 V when you apply a voltage of less than VSS to the input pins. With a voltage down to VSS – 0.5 V, damage should not occur.

A current pass does not exist between the input pins and VDD because there is no protection device between them. The device should not be damaged as long as the input voltage is less than VSS + 7 V when you apply a voltage of more than VDD to the input pins.

It depends on the individual product.
Please refer to our data sheet.

It depends on the invidual product. Please refer to our data sheet.

Acceleration tests, which are included in periodic reliability tests, are performed for a time equivalent to the product life, to judge the endurance of the product.
Voltage acceleration and temperature acceleration are included in the acceleration tests. ABLIC adopts temperature acceleration tests based on the Arrhenius model.
The acceleration factor conforms to JEITA standard EIAJ ED-4701 and is calculated by the following formula.

(Acceleration factor calculation formula) L = exp(Ea/kT2)/exp(Ea/kT1)
L: Acceleration factor
Ea: Energy of activation
k: Boltzmann coefficient
T2: Actual use temperature (absolute temperature)
T1: Acceleration test temperature (absolute temperature)

Specifically, the following conditions are substituted.
Energy of activation 0.5 eV
Boltzmann coefficient 8.617 × 10-5 eV/K
Actual use temperature 40°C
As a result of the above substitution, the acceleration factor at 125°C is shown to be 52 times that at 40°C. In sum,
1,000 hours are equivalent to 5.9 years
2,000 hours are equivalent to 11.8 years.

As shown above, successfully performing reliability tests at 125°C for 2,000 hours assures that the product life is judged to be at least 10 years at the actual use temperature.

Inorganic phosphorus is not used in ABLIC products. Organic phosphorus is used in some packages as a resin hardness accelerator.

The power dissipation is the average power per second.
Packages can be used when the average power is within the power dissipation range, even if a large current momentarily flows due to rush current.

Radiation pads on the rear side are affixed to the IC die substrate via silver paste (conductive paste). Radiation pads, therefore, must be used with the potential of the pads being the same as that of the IC die substrate or floating.

*Caution Radiation pads cannot be used as electrodes.