As long as the output signal is high, the CD pin stays at the GND level because capacitance C is discharged, so a reset does not occur even if the CD pin is made low. To activate external reset, forcibly make the OUT pin low. The following shows an example of an external reset circuit.

The delay time (power-on clear time) can be calculated by substituting the constant to the following equation when the power-on clear circuit is structured by series S-808XXCN or S-1000NXX:

Caution: To avoid oscillation: Use a resistor of 75 kΩ or lower for the S-808XXCN. Use a resistor of 75 kΩ or lower and capacitor of 0.01 µF or higher for the S-1000NXX. When a capacitor is not connected to the S-1000NXX, use a resistance of 800 Ω or lower. The S-809XXC Series and S-801 Series each have a built-in delay circuit, so a power-on clear circuit can be easily configured. See the respective data sheets for details. The detector may momentarily output “H” in an uncertain area at the minimum operating voltage or less, depending on the startup speed of the power supply voltage.

Since the output is configured of a MOSTr, device destruction due to thermal runaway as in bipolar transistors can be avoided. However, note that the devices will be destroyed if a current that surpasses tolerable losses of the package flows due to a short circuit with VDD or to connection of a super capacitor. Nch Open Drain Short Circuit with VDD2

Nch Open Drain Short Circuit with VDD2

Using the S-80960AL as an example, a case in which tolerable losses are surpassed is explained. Based on the Iout-Vds characteristic in the data sheet, a current of about 50mA flows to Output NchTr in case 5V is impressed to the output when VDD = 6V. The loss at this time will be P = 5(V) x 50(mA) = 250mW, exceeding the absolute maximum rating of 150mW. In a worst case, the devices may be destroyed.

The operation when Vin fluctuates near detection and release voltages is explained in Fig. 1 using the output of CMOS (active L) as an example.

1. OUT outputs ‘L’ and becomes ready to detect when VDD falls below -Vdet. Since the comparison voltage with VDD is changed to +Vdet, a release state is not set if voltage VDD is below +VPET even when VDD rises and fluctuates near -Vdet. (During period “A”)

2. The comparison voltage with VDD is changed to -Vdet when VDD rises and exceeds +Vdet. Therefore, detection is not performed even when Vin fluctuates near +Vdet unless it lowers below -Vdet. OUT will output ‘H’ after a release delay time (td) and will change to a release state. (During period “B”)

The condition of the output will become high impedance in case of open drain output.

Generally, the discharging diode D discharges charges in the release delay capacitor through it in a CR resetting circuit illustrated in Fig. 1, to ensure a sufficient release delay time during release. The S-809XXC discharges charges in the release delay capacitor in the discharge circuit inside the IC except during release delay operation as shown in Fig. 2. Therefore, an external discharge diode is not required. Figure 1: Function of Discharging Diode (Ordinary CR resetting)

A reset signal cannot be generated even when Pin CD is forcibly connected to GND by an external SW as shown in Fig. 1. A circuit configuration that generates a reset signal cannot be obtained even if Pin CD is forcibly connected to GND as illustrated by the block diagram in Fig. 2. As shown in Fig. 2, the level of Pin CD is normally a GND level. Triggering occurs only when VDD exceeds the release voltage, causing charging of the capacitor for release delay connected to Pin CD to start, which in turn raises the voltage. The level of Pin OUT will become Hi (HiZ for Nch products) when the voltage reaches a certain level, to provide a release delay time. After clearing resetting, the capacitor for release delay will be discharged immediately to reset it to the GND level.

If a high output level at a minimum operational voltage presents a problem, it can be solved by externally mounting a Pch transistor.

In case VDD lowers below the detection voltage, the Nch open drain output will turn on and the level of OUT will become low. When VDD lowers below the threshold value of the external PchTr, the external PchTr will turn off and Rup resistance will be separated from VDD, so that VDD lowers below the MIN value of operational voltage of the voltage detector. Therefore, the level of OUT will not become high (VDD) even though NchTR no longer operates. As a precaution when selecting an external PchFET, select one whose threshold voltage is higher than the minimum operational voltage of the voltage detector. Note that the output (OUT) will not become VSS in this case.

Shown below are examples of circuits that illustrate how to widen the hysteresis range in an application that uses a detection voltage alteration circuit.

Looking at Figure 1, Diode D1 will be needed to prevent a reverse current from RUP to R2 and to R3. Let us assume that the detection voltage in IC setting to be -Vdet, hysteresis in IC setting, VHYS, and forward voltage of D1, Vf. When detection is made, the voltage obtained by dividing VDD by R1 and R3 is compared with the detection voltage in IC setting,

When VDD lowers below the operational detection voltage and the level of the output becomes low, the circuit illustrated in Fig. 1 will become equivalent to the circuit shown in Fig. 3.

Figure 3: Equivalent circuit when VDD is below operational detection voltage

In a detection state, R2 and Vf are input to R3 in parallel and the operational release voltage and operational hysteresis range will become as follows

The same values can be used with the circuit illustrated in Fig. 2 also.

As a precaution for R1 and R2 setting values, R1 < 75kΩ should be set as a countermeasure for oscillation. Detection voltage will deviate by current consumption x R1 voltage the larger R1 is, to deteriorate the detection accuracy. Therefore, set values for R1 and R2 are recommended to be as small as possible (about several kΩ).

Shown below is an example of a circuit that illustrates how to widen the hysteresis range by increasing the release voltage only while maintaining the detection voltage as set in the IC when power sources for input and output are different.

Figure 1: Nch Open Drain Output
Output is pulled up to VDD2 where VDD2 > VDD1

Diode D1 will be needed to prevent a reverse current flowing from VDD2 to VDD1. Assuming that the detection voltage in IC setting to be -VDET, hysteresis in IC setting, VHYS, and forward voltage of D1, Vf:

As a precaution for R1 and R2 setting values, R1 < 75kΩ should be set as a countermeasure for oscillation. Detection voltage will deviate by current consumption x R1 voltage the larger R1 is, to deteriorate the detection accuracy. Therefore, set values for R1 and R2 are recommended to be as small as possible (about several kΩ).

In case a voltage detector with a desired hysteresis range is not available, increase the release voltage by installing an external circuit, to widen the hysteresis range. The following illustration shows an example of a circuit that widens the hysteresis range.

Figure 1: Nch Open Drain Output
Output is pulled up to VDD

Assuming that the detection voltage in IC setting in the circuit illustrated in Fig. 1 to be -V_DET and hysteresis range in IC setting, V_HYS:

Figure 2

As a precaution for R1 and R2 setting values, R1 < 75kΩ should be set as a countermeasure for oscillation. Detection voltage will deviate by current consumption x R1 voltage the larger R1 is, to deteriorate the detection accuracy. Therefore, the set values for R1 and R2 are recommended to be as small as possible (about several kΩ).

There are two cautions when the pull-up resistance is increased:
Caution 1: Output voltage (Hi is output by pull-up resistance) when the voltage detector is off is lowered by an off-leak current. Caution 2: The output pin (input pin in second stage) becomes less robust to noise.

Figure 1: Voltage detector is off

Caution 1:
Fig. 1 illustrates the circuit of the Nch open drain output product. When the voltage detector is off, M1 turns off and Pin OUT outputs Hi (VDD) due to the external pull-up resistance Rup. At this time, Off-Leak Current ILEAK flows to M1, generating a voltage drop (Vdwn) of ILEAK x Rup at both ends of the pull-up resistance Rup. Thus, the voltage at Pin OUT will be as follows:

Vout = VDD −Vdwn = VDD − I LEAK × Rup

Using the S-808XXC as an example, the data sheet shows maximum ILEAK = 0.1µA. If Rup = 10MΩ, the voltage drop Vdwn at Rup will be:

Vdwn = 0.1(µA) × 10(MΩ) = 1(V)

The voltage Vout will be low as much as 1V compared with VDD so that Level Hi may not be recognized at the input of the connect-to IC.

Caution 2:
The impedance at Pin OUT will be high and the output pin will become less robust to noise and error setting may be applied.

Based on the foregoing cautions, the recommended Rup value is 100kΩ.

There are two cautions when the pull-up resistance is decreased:
Caution 1: Output pin voltage is increased during detection.
Caution 2: Current that flows in the pull-up resistance increases (Increase in current consumption as viewed from the battery side during detection).

Caution 1:
When the level of VDD lowers below the detection voltage, OUT = ‘L’ is output and the internal output NchTr turns on. At this time, voltage that is obtained by dividing power supply voltage VDD by the pull-up resistance and ON resistance of NchTr is output to the output. Therefore, Level ‘L’ increases when the pull-up resistance is too small.
Using the case of VDD = 2.4V in the S-80860CN as an example, the difference in output voltage of Level ‘L’ between 10kΩ and 1kΩ in pull-up resistance between OUT and VDD is explained. As shown in Figs. 2 and 3, output voltage is calculated based on the data at the intersection point between the Vds-Id characteristic of M1 (described in data sheet of S-808XXC Series) and load curve of pull-up resistance. Fig. 3 is an enlarged diagram of the shaded part in Fig. 2. Reading output voltage based on the data at the intersection point between the Vds-Id characteristic (blue curve) and load curve of 10kΩ pull-up resistance (red curve) in Fig. 3, the output voltage is about 20mV and is about 200mV with the 1kΩ pull-up curve (aqua color). Level ‘L’ with 1kΩ is about 10 times higher compared with 10kΩ pull-up. No problem will arise if this Level ‘L’ is a level that is recognized as ‘L’ at the input of the connected-to IC of the voltage detector. However, if the pull-up resistance value is too small and Level ‘L’ is too high, the level of ‘L’ will no longer be recognized at the output of the connect-to IC.

Caution 2:
As in Caution 1, reading the output current (current that flows through Rup) based on the data at the intersection point between the load curves of pull-up resistances and Vds-Id characteristic shown in Fig. 3, the output current is about 0.22mA at 10kΩ compared with about 2.2mA at 1kΩ, or about 10 times higher. The current consumption as viewed from the battery side during detection operation increases.

Based on the foregoing cautions, the recommended Rup value is 100kΩ.

ABLIC’s datasheet describes that an error pulse generates in the power-on reset circuit due to an uncertain area characteristic at the sharp rising edge of the power supply. See the figure given below. To take an easy and simple preventive measure against occurrence of an error pulse, it is only necessary to add a resistor to the power-on reset circuit. The following are an error pulse generation mechanism and preventive measures.

Error Pulse Generation Mechanism

Figure 1: Power-on Reset Circuit Listed in the Datasheet

In general, an uncertain area exists in the V/D. Further reduction in V/D input voltage “Vin” fails to flow “Rup” current, and eventually V/D output voltage “Vout” becomes not inherent LO but HI. The power-on reset circuit leads to the delay in the rise in V/D input voltage “Vin” by RC time constant at the time of powering on Vdd and also leads to the delay in the time release signal necessary to reach V/D release voltage “Vdet+.” However, V/D input voltage “Vin” passes through the uncertain area which does not flow current of the output pull up resistance Rup. This results in output of an error pulse as a release signal.

Acceleration tests, which are included in periodic reliability tests, are performed for a time equivalent to the product life, to judge the endurance of the product.
Voltage acceleration and temperature acceleration are included in the acceleration tests. ABLIC adopts temperature acceleration tests based on the Arrhenius model.
The acceleration factor conforms to JEITA standard EIAJ ED-4701 and is calculated by the following formula.

(Acceleration factor calculation formula) L = exp(Ea/kT2)/exp(Ea/kT1)
L: Acceleration factor
Ea: Energy of activation
k: Boltzmann coefficient
T2: Actual use temperature (absolute temperature)
T1: Acceleration test temperature (absolute temperature)

Specifically, the following conditions are substituted.
Energy of activation 0.5 eV
Boltzmann coefficient 8.617 × 10-5 eV/K
Actual use temperature 40°C
As a result of the above substitution, the acceleration factor at 125°C is shown to be 52 times that at 40°C. In sum,
1,000 hours are equivalent to 5.9 years
2,000 hours are equivalent to 11.8 years.

As shown above, successfully performing reliability tests at 125°C for 2,000 hours assures that the product life is judged to be at least 10 years at the actual use temperature.

Inorganic phosphorus is not used in ABLIC products. Organic phosphorus is used in some packages as a resin hardness accelerator.

The power dissipation is the average power per second.
Packages can be used when the average power is within the power dissipation range, even if a large current momentarily flows due to rush current.

Radiation pads on the rear side are affixed to the IC die substrate via silver paste (conductive paste). Radiation pads, therefore, must be used with the potential of the pads being the same as that of the IC die substrate or floating.

*Caution Radiation pads cannot be used as electrodes.